1. Field of the Invention
The present invention particularly relates to an organic electroluminescence (EL) display or other image display device comprising pixel circuits having electro-optical elements controlled in luminance by a current value arranged in a matrix, in particular a so-called active matrix type image display device wherein the value of the current flowing through an electro-optical element is controlled by an insulating gate type field effect transistor provided inside each pixel circuit.
2. Description of the Related Art
In an image display device, for example, a liquid crystal display, an image is displayed by arranging a large number of pixels in a matrix and controlling a light intensity for every pixel in accordance with image information to be displayed. The same is true for an organic EL display etc., but an organic EL display is a so-called self light emitting type display which has light emitting elements in the pixel circuits and has the advantages that the viewability is high in comparison with a liquid crystal display, no backlight is required, a response speed is high, etc. Further, it greatly differs from a liquid crystal display etc. in the point that the luminance of each light emitting element is controlled by the value of the current flowing through it to give tones of the emitted colors, that is, the light emitting elements are current controlled types.
An organic EL display, in the same way as a liquid crystal display, may be driven by the simple matrix system and the active matrix system, but while the former is simple in structure, but has problems such as the difficulty of realization of a large scale and high definition display. For this reason, there has been active development of the active matrix system controlling the current flowing through the light emitting element inside each pixel circuit by an active element provided inside the pixel circuit, generally, a thin film transistor (TFT).
FIG. 1 is a block diagram of the configuration of an organic EL display device employing the current driving system. This display device 1 has, as shown in FIG. 1, a pixel array 2 comprised of pixel circuits (PXLC) 2a arrayed in an m×n matrix, a horizontal selector (HSEL) 3, a write scanner (WSCN) 4, a drive scanner (DSCN) 5, data lines DTL1 to DTLn to which data signals selected by the horizontal selector 3 and in accordance with the luminance information are supplied, scanning lines WSL1 to WSLm selectively driven by the write scanner 4, and drive lines DSL1 to DSLm selectively driven by the drive scanner 5.
FIG. 2 is a circuit diagram of an example of the configuration of a pixel circuit 2a of FIG. 1.
The pixel circuit 2a of FIG. 2 has p-channel thin film field effect transistors (hereinafter referred to as TFT) 11 to 14, a capacitor C11, and a light emitting element constituted by an organic EL element (OLED) 15. Further, in FIG. 2, DTL shows a data line through which the input signal is propagated as current. An organic EL element often has a rectification property, so is sometimes referred to as an organic light emitting diode (OLED). In FIG. 2 and the other figures, use is made of the symbol of a diode as the light emitting element, but in the following explanation, a rectification property is not always required from the OLED. In FIG. 2, a source of the TFT 11 is connected to a power supply potential VCC (supply line of power supply voltage VCC), while a cathode of the light emitting element 15 is connected to a ground potential GND. The pixel circuit 2a of FIG. 2 operates as follows.
At the time of writing an input signal (current signal) SI, the TFT 13 and the TFT 14 are held in a conductive state in the state holding the TFT 12 in a nonconductive state. Due to this, a current in accordance with the signal current flows through tthe drive transistor constituted by the TFT 11. At this time, a gate and a drain of the TFT 11 are electrically connected by the TFT 13 in the conductive state, and the TFT 11 is driven in a saturation region. Accordingly, the gate voltage corresponding to the input current is written based on the following equation 1 and held in the pixel capacitance constituted by the capacitor C11. Thereafter, the TFT 14 is held in the nonconductive state, and the TFT 12 is held in the conductive state. Due to this, a current in accordance with the input signal current flows through the TFT 12 and the light emitting element 15, whereby the light emitting element 15 emits light with a luminance in accordance with the current value. As described above, the operation for turning on the TFT 14 to transfer the luminance information given to the data line to the inside of a pixel will be referred to as “writing” below.
In this pixel circuit 2a, variation in a threshold value Vth and mobility μ of the drive transistor 11 are corrected.Ids=½·μ(W/L)Cox(Vgs−|Vth|)2  (1)
Here, μ indicates the mobility of the carrier, Cox shows a gate capacitance per unit area, W shows a gate width, L shows a gate length, Vgs shows a gate-source voltage of the TFT 11, and Vth indicates the threshold value Vth of the TFT 11.
In this system, a video signal is input as the current value Iin to the horizontal selector 3 of the panel. The input current signal is sampled and held at the horizontal selector 3. After all stages are sampled and held, the current value is simultaneously output to the data lines DTL to which the pixels are connected.
FIG. 3 is a circuit diagram of the configuration of principal parts of the horizontal selector 3. The horizontal selector 3 has, as shown in FIG. 3, current sample and hold circuits 31-1, 31-2, . . . , and 31-n provided corresponding to the data lines DTL1, DTL2, . . . , and DTLn laid for every column of the matrix array of the pixel circuits and supplied with data signals in accordance with the luminance information and horizontal switches (HSWs) 32-1, 32-2, . . . , and 32-n formed by n-channel TFTs.
The current sample and hold circuit 31-1 has, as shown in FIG. 3, a TFT 33-1, TFT 34-1, TFT 35-1, a capacitor C31-1, and nodes ND31-1 and ND32-1. In the same way as the above, the current sample and hold circuit 31-1 has, as shown in FIG. 3, a TFT 33-2, TFT 34-2, TFT 35-2, a capacitor C31-2, and nodes ND31-2 and ND32-2. Then, although not illustrated, the current sample and hold circuit 31-n has a TFT 33-n, TFT 34-n, TFT 35-n, a capacitor C31-n, and nodes ND31-n and ND32-n.
The sample and hold operation of this horizontal selector 3 will be explained in relation to FIGS. 4A to 4M. Note that the SHSW of FIG. 4A shows a switch signal of the horizontal switch. Further, FIG. 4H shows a drain potential Vd331 of the first column TFT 33-1, FIG. 4I shows a drain potential Vd332 of the second column TFT 33-2, FIG. 4J shows a drain potential Vd33n of the n-th column TFT 33-n, FIG. 4K shows a potential VC111 of the first column capacitor C11-1, FIG. 4L shows a potential VC112 of the second column capacitor C11-2, and FIG. 4M shows a potential VC11n of the n-th column capacitor C11-n.
As shown in FIG. 4A, in a state where the switch signal SHSW is set at the low level and all horizontal switches HSW are turned off, as shown in FIGS. 4B and 4C, the sample and hold lines SHL31-1 and 32-1 to which the TFT 34-1 and TFT 35-1 of the first column current sample and hold circuit 31-1 are connected are set at the high level to place the TFT 34-1 and TFT 35-1 in the conductive state (turn them on). At this time, the input signal current Iin flows in the current sample and hold circuit 31-1. At this time, the TFT 33-1 is connected at a gate and a drain via the TFT 34-1, so operates in the saturation region. The gate voltage thereof is determined based on above equation 1 and, as shown in FIG. 4K, it is held in the capacitor C31-1. After the predetermined gate voltage is written into the capacitor C31-1, the sample and hold line SHL31-1 is set at the low level and the TFT 34-1 is placed in the nonconductive state. Thereafter, the sample and hold line SHL32-1 is placed in the low level, and the TFT 35-1 is placed in the nonconductive state.
Next, in the same way, as shown in FIGS. 4D and 4E, by making the sample and hold lines SHL31-2 and 32-2 to which the TFT 34-2 and TFT 35-2 of the second column current sample and hold circuit 31-2 are connected the high level, the TFT 34-2 and TFT 35-2 are placed in the conductive state (turned ON). At this time, the input signal current Iin flows through the current sample and hold circuit 31-2. At this time, the TFT 33-2 is connected at a gate and a drain via the TFT 34-2, so operates in the saturation region. The gate voltage thereof is determined based on the above equation 1 and, as shown in FIG. 4L, is held in the capacitor C31-2. After the predetermined gate voltage is written into the capacitor C31-2, the sample and hold line SHL31-2 is placed at the low level and the TFT 34-2 is placed at the nonconductive state, then the sample and hold line SHL32-2 is placed at the low level and the TFT 35-2 is placed at the nonconductive state. After this, the adjacent sample and hold circuits sequentially operate, and video signals Iin are point sequentially sampled and held in all circuits. Thereafter, as shown in FIG. 4A, all stages of the horizontal switch HSW are simultaneously turned ON, the TFT 33-1 to TFT 33-n act as constant current sources, and, as shown in FIG. 5, the sampled and held current values are output to the data lines DTL1 to DTLn.
In the above horizontal selector 3, however, there is the disadvantage that the drain potential of a TFT 33(-1 to -n) functioning as a constant current source, particularly the drain potential of a TFT 33 for which a sample and hold operation was previously carried out falls, therefore it can not be held constant. This problem will be explained in further detail next.
Here, the potential of each node at the time of sampling and holding of the first column current sample and hold circuit 31-1 will be investigated. In the current sample and hold circuit 31-1, as shown in FIG. 6A, the TFT 35-1 is held in the nonconductive state to sample and hold the input current Iin. During this period, the TFT 33-1 is continuously on, so the drain potential of the TFT 33-1 (potential of the ND31-1) loses its supply source and falls to the ground potential GND level. At this time, note the TFT 34-1. The TFT 34-1 is turned off, and the gate potential corresponding to the current Iin is held in the capacitor C31-1.
However, due to the potential of the node ND31-1 dropping to the ground potential GND level, the TFT 34-1, as shown in FIG. 6B, ends up being supplied with the drain-source voltage Vds, and a leakage current flows through the TFT 34-1. Due to the leakage current flowing out from the capacitor C31-1, the gate voltage of the TFT 33-1 is reduced. Due to this, the gate-source voltage Vgs of the TFT 33-1 ends up being reduced from that at the time of the sampling and holding. Even if the horizontal switch HSW turns on and becomes the saturation state thereafter, only a current having a value smaller than the current Iin ends up flowing. This leakage amount is proportional to a leakage time.
The sample and hold circuit operates point sequentially as mentioned above, therefore the time during which the gate potential is held in each capacitor differs between a scanning start part and a scanning end part. Namely, as shown in FIGS. 4K to 4M, the holding time becomes longer at the scanning start part in comparison with the end part. For this reason, the leakage time becomes longer and the drop in the gate voltage becomes larger at the scanning start part in comparison with the scanning end part. That is, even with a single colored raster display over the entire screen, as shown in FIG. 7, the luminance ends up with gradation toward the scanning end part. Particularly, the leakage current is high in a TFT for driving an organic EL etc., so this problem conspicuously appears.
This problem can occur at any time when sampling a current regardless of the fact the display is an organic EL. For example, when sampling the current point sequentially and outputting the results all together, for the same reason, the current value of the output ends up differing between the sampling start part and the end part.